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| rev. 1.1 12 / 2010 page 1 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 prm? regulator features description ? 45 v (38 to 55), non-isolated zvs buck-boost regulator ? 5 to 55 v adjustable output range ? building block for high efficiency dc-dc systems ? 400w output power in 1.1 in 2 footprint ? 97% typical efficiency, at full load ? 1,360 w/in 3 (83 w/cm 3 ) power density ? enables a 48 v to 1.5 v, 230 a isolated, regulated solution with total footprint of 3.3 in 2 (21 cm 2 ) ? flexible ?remote sense? architecture optimizes regulation / feedback loop design to fit application requirements ? current feedback signal allows dynamic adjustment of current limit setpoint ? 3.61 mhrs mtbf (mil-hdbk-217plus parts count) typical applications ? high efficiency server processor and memory power ? high density ate system dc-dc power ? telecom npu and asic core power ? led drivers ? high density power supply dc-dc rail outputs ? non-isolated power converters the v?i chip? prm? regulator is a high efficiency converter, operating from a 38 to 55 vdc input to generate a regulated 5 to 55 vdc output. the zvs buck ? boost topology enables high switching frequency (~1 mhz) operation with high conversion efficiency. high switching frequency reduces the size of reactive components enabling power density up to 1,360 w/in 3 . the full v?i chip package is compatible with standard pick- and-place and surface mount as sembly processes with a planar thermal interface area and superior thermal conductivity. in a factorized power architecture? system, the PRM48BF480T400A00 and downstream vtm? current multiplier minimize distribution and conversion losses in a high power solution. an external control loop and current sensor maintain regulation and enable flexibility both in the design of voltage and current compensation loops to control of output voltages and currents. pr pc tm +in -in if re sg vc -out +out load 38 to 55 vdc input current sense enable/ disable feedback voltage reference voltage control pc +in -in vc +out1 +out2 -out1 -out2 pc +in -in vc +out1 +out2 -out1 -out2 constant vc 48 v to 1.5 v , 230a v olta g e re g ulato r prm tm regulator vtm tm current multi p lie r vtm tm current multi p lie r
rev. 1.1 12 / 2010 page 2 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 1.0 absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to device. electrical specifications do not apply when operating beyond rated operating conditions. all voltages are specified relative to sg unless otherwise noted. po sitive pin current represents cu rrent flowing out of the pin. min max unit -0.3 10.5 v 10 ma -0.3 5.7 v 10 ma -0.3 5.7 v 1 m a -1 62 v -0.5 10.5 v 100 ma 100 ma -0.5 5.7 v -0.3 5 v -0.5 18 v 1.8 a -1 62 v 11 a -40 125 oc -40 125 oc +in to ?in ???????????????????????????.. vc to ?out ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? ????????????????????????????? if +out to ?out vs re ????????????????????????????? sg pr pc tm ???????????????????????????.. ???????????????????????????.. ???????????????????????????.. ????????????????????????????? ???????????????????????????.. operating analog ic junction temperature storage temperature ????????????????????????????? output current 2.0 electrical characteristics specifications apply over all line and load conditions, t j = 25 oc and output voltage from 20v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of -40 oc < t j < 125 oc (t-grade). attribute s y mbol min t y pmaxunit power input specification input voltage range v in 38 45 55 v v in slew rate d v in / dt 0.001 1000 v /ms no load power dissipation p nl 2.4 4 w input quiescent current i qc 4.5 8.5 ma input current i in dc 10.9 11.0 a input capacitance (internal) c in int 4 ? f input capacitance (internal) esr r cin 1.5 m ? power output specification output voltage range v out 5 48 55 v output current i out 8.33 a output power p out 400 w 10 % 24 % 35 % 96.5 97.4 % 94.8 % 90.0 % output discharge current i od 13 ma output voltage ripple v out pp 960 1500 mv output inductance (parasitic) l out par 1.9 nh output capacitance (internal) c out int 4 ? f output capacitance (internal) esr r cout 1.5 m ? powertrain protections input undervoltage turn-on v in uvlo+ 35.75 37.13 v input undervoltage turn-off v in uvlo- 31.97 33.56 v input overvoltage turn-on v in ovlo+ 55.91 57.24 v input overvoltage turn-off v in ovlo- 58.44 59.91 v overcurrent (if) and input over/undervoltage blanking time t blnk 50 120 150 ? s output overvoltage threshold v out ovlo+ 55.25 56.57 59.04 v thermal shutdown setpoint t jotp 130 oc overtemperature, output overvoltage and pc shutdown response time t prot 2 ? s short circuit vout threshold v sc vout 3.0 v short circuit vout recovery threshold v sc voutr 4.0 v short circuit vpr threshold v sc vpr 7.2 v short circuit vpr recovery threshold v sc vprr 7.1 v short circuit timeout t sc 20 ms short circuit recovery time t scr 0.1 ms output power limit p prot 400 w conditions / notes output turn-on delay >50% load; over temperature equal input, output and pr voltage at full load; over line and trim, with 25c < t c < 100c but negligible part-part temp mismatch see fig.16, soa see fig.16, soa 0 < v in < 18 v pc high, v in = 45 v instantanous powertrain shutdown, latched after t blnk instantanous powertrain shutdown, latched after t blnk short circuit fault latched after v sc_vout and v sc_vpr thresholds persist for this time effective value, v in = 45 v (see fig. 20) from v in applied, pc floating pc low, v in = 45 v i out = 8.33a, v in = 38 v, v out = 48 v ? s frequency @ 1 mhz, simulated j-lead model c out_ext = 0 f, i out = 8.33 a, v in = 45 v, v out = 48 v, 20 mhz bw 20 from pc pin release, v in applied, t off expired effective value, v out = 48 v (see fig. 20) nominal line, full load, v out = 48v t on 50% load and v out = 48 v; over temperature section 4.0 current sharing difference (exclusive of current limit) i out_share equal input, output and pr voltage at full load; v in = 45 v, v out = 48 v equal input, output and pr voltage at full load; over line and trim, with 25c < tc < 100c and <= 75c part-part temp. mismatch (worst case) efficiency instantaneous, latched shutdown instantaneous, latched shutdown; guaranteed by design, not production tested; v tm = 4.03v rev. 1.1 12 / 2010 page 3 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 3.0 signal characteristics specifications apply over all line and load conditions, t j = 25 oc and output voltage from 20v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of -40 oc < t j < 125 oc (t-grade). primar y control pc signal type state attribute s y mbol conditions / notes min t y pmaxunit pc voltage v pc 4.7 5 5.3 v pc available current i pc_op 1.8 ma pc source current i pc_en after t off 90 ? a minimum time to start t off section 5.0 10.0 18.0 30.0 ms startup pc enable threshold v pc_en 2.50 3.20 v pc disable threshold v pc_dis 1.75 2.40 v pc resistance (external) r pc_ext resistance to sg required to disable the prm 300 ? digital output [short circuit fault] fault pc sink current to sg i pc_sc short circuit, pc voltage 1 v or above 25 ma digital output [all other faults] fault pc sink current to ~1v i pc_fault tempature, over- and undervoltage, overcurrent 10 ?? ? the pc pin enables and disables the prm ? in prm array configurations, pc pins should be connected in order to synchronize startup. ? it is a weak pull-down during any fault mode excluding short circ uit. pc is a strong pull-down to sg if a short circuit fault is latched. regular operation standby startup analog output digital input / output v olta g e source v s signal type state attribute s y mbol conditions / notes min t y pmaxunit vs voltage v v s 8.55 9.00 9.45 v vs available current i v s 5 ma vs voltage ripple v vs_pp iout = 0a, cvs_ext=0. maximum specification includes powertrain operation in burst mode. 100 400 mv vs capacitance (external) c v s_ext 0.04 ? f vs fault response time t fr_vs from fault recognition to vs = 1.5 v 30 ? s regular operation analog output ? intended to power feedback components and/or auxiliary circuits. ? 9 v, 5ma regulated voltage source ? with > 5% output load, vs ripple typically 100mv transition reference enable re signal type state attribute s y mbol conditions / notes min t y pmaxunit re voltage v re 3.0 3.3 3.6 v re available current i re 8.0 ma re regulation % re across load and temperature ? 2.5 % re voltage ripple v re_pp in burst mode 100 mv pc to re delay t pc_re fault detected 100 ? s re capacitance (external) c re_ext 0.1 ? f vs to re delay t vs_re vs = 8.1 v to re high, v in > v in_uvlo- 1 ms transition regular operation ? re signals successful startup and a powertrain that is ready for operation ? regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor analog output control node pr signal type state attribute s y mbol conditions / notes min t y pmaxunit pr voltage active range v pr 0.79 7.40 v pr source current i pr v pr ? 0.79v 2 ma pr sink current i pr_low v pr ? 0.79v 250 500 750 ? a pr resistance to sg r pr 93.3 k ? analog input ? modulator control node input ? sinks constant current when ex ternally driven in active range ? sources current when pulled below active range regular operation current feedback if signal type state attribute s y mbol conditions / notes min t y pmaxunit current limit (clamp) threshold v if_il v in = 45 v; t j = 25 c 1.90 2.00 2.10 overcurrent protection threshold v if_oc not production tested; guaranted by design; t j = 25 c 2.58 2.69 2.80 if input impedance r if 2.11 2.13 2.15 k ? current limit bandwidth bw il 2 khz ? a voltage proportional to the prm output current must be supplied externally to the if pin in order for the device to properl y protect overcurrent events and to enable output current limit (clamp) ? overcurrent protection trip will cause instantaneous powertrain disable, latched after t blnk analog input v regular operation rev. 1.1 12 / 2010 page 4 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 temperature monito r tm signal type state attribute s y mbol conditions / notes min t y pmaxunit tm voltage v tm full temperature range 2.12 4.04 v tm voltage reference v tm_amb t j = 27 c 2.94 3.00 3.06 v tm voltage ripple v v s_pp powertrain in burst mode 200 mv tm available current i tm 100 ? a tm gain a tm 10 mv/c digital output [fault flag] fault or standby tm disabled current i tm_dis dc state with tm voltage +/- 0.5v. this is a high impedance state. 0.0 ma ? the tm pin monitors the internal temperature of the prm analog control ic. ? "power good" flag to verify that the prm is operating analog output regular operation si g nal ground sg signal type state attribute s y mbol conditions / notes min t y pmaxunit analog input / output any maximum allowable current i sg -100 100 ma ? all control signals must be referenced to this pin, with the exception of vc ? sg is internally connected to -in and -out v tm control v c signal type state attribute s y mbol conditions / notes min t y pmaxunit vc voltage v vc r vc_ext = 68 ? 13 v vc available current i vc v c <=14 v, v in > 20 v 200 ma vc duration t v c 7 10 16 ms vc slew rate dvc/dt r vc = 1k ? 20 v/ ? s ? pulsed voltage source used to power and synchronize downstream vtm ? if not used, must be resistively terminated to -out analog output startup rev. 1.1 12 / 2010 page 5 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 4.0 functional block diagram +vout -vout +vin tm pc temperature dependent voltage source -vin v pc_en 100ua 5v 2ma max 16v internal vcc regulator 3v vref (130c) fault logic t off delay r l overtemperature protection modulator enable q1 q2 q3 q4 cout cin pr 0.5ma 2.5ma min 9v vin (ov, uv) vout (ov) if current limit overcurrent protection v if_il v if_oc 8.2v re 3 v @ 27c re vc vtm vc start up pulse vs 9v 0.01uf sg uc 8051 3.3v linear regulator pc re vout var. vclamp vcc 14v 10ms +vout output discharge (od) 3.3v vcc 3.3v instant latch latch after 120us pr q q set clr s r 10ua vcc 93.3k pc pr enable rev. 1.1 12 / 2010 page 6 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 5.0 high level functional state diagram conditions that cause state transitions are shown along arro ws. sub-sequence activities listed inside the state bubbles. rev. 1.1 12 / 2010 page 7 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 6.0 timing diagrams module inputs are shown in blue ; module outputs are shown in brown ; timing diagrams assumes the following: ? single prm (no array) ? vs powers error amplifier ? re powers voltage reference a nd output current transducer ? i out is sensed, scaled, and fed back to if pin such that if = 2.00 v at full load re v out pc pr v in vc vs tm if input input / output output uv ov vpc_en vpc vvc vpr_max vvs_amb vtm_amb vre_amb t vc vif_oc t blnk 1 start up with 1.2v/ms < dv in /dt < maximum vpr_min t < t blnk ov 2 quick oc (t rev. 1.1 12 / 2010 page 10 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 efficiency & power dissipation v out = 55 v t case = -40 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 4 6 8 10 12 14 16 18 power dissipation [w] 38 45 55 38 45 55 v in : figure 5 ? total efficiency and power dissipation vs. v in and i out , v out = 55 v, t case = -40oc efficiency & power dissipation v out = 48 v t case = 25 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 2 4 6 8 10 12 14 16 power dissipation [w] 38 45 55 38 45 55 v in : figure 7 ? total efficiency and power dissipation vs. v in and i out , v out = 48 v, t case = 25oc efficiency & power dissipation v out = 20 v t case = 100 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 2 4 6 8 10 12 14 16 power dissipation [w] 38 45 55 38 45 55 v in : figure 9 ? total efficiency and power dissipation vs. v in and i out , v out = 20 v, t case = 100oc efficiency & power dissipation v out = 20 v t case = 25 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 2 4 6 8 10 12 14 16 power dissipation [w] 38 45 55 38 45 55 v in : figure 6 ? total efficiency and power dissipation vs. v in and i out , v out = 20 v, t case = 25oc efficiency & power dissipation v out = 55 v t case = 25 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 4 6 8 10 12 14 16 18 power dissipation [w] 38 45 55 38 45 55 v in : figure 8 ? total efficiency and power dissipation vs. v in and i out , v out = 55 v, t case = 25oc efficiency & power dissipation v out = 48 v t case = 100 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 2 4 6 8 10 12 14 16 power dissipation [w] 38 45 55 38 45 55 v in : figure 10 ? total efficiency and power dissipation vs. v in and i out , v out = 48 v, t case = 100oc rev. 1.1 12 / 2010 page 11 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 efficiency & power dissipation v out = 55 v t case = 100 oc 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 0123456789 load current [a] efficiency [%] 4 6 8 10 12 14 16 18 power dissipation [w] 38 45 55 38 45 55 v in : figure 11 ? total efficiency and power dissipation vs. v in and i out , v out = 55 v, t case = 100oc figure 13 ? typical output voltage ripple waveform, t case = 30oc, v in = 45 v, v out = 48 v, i out = 8.33 a, no external capacitance. powertrain switching frequency and periodic input charge vs. input voltage - full load 800 825 850 875 900 925 950 975 1000 1025 38 40 42 44 46 48 50 52 54 56 input voltage [v] f sw [khz] 0 4 8 12 16 20 24 28 32 36 total input charge per switching cycle [ ? c] 55 20 48 55 20 48 v out f sw ? c figure 15 ? powertrain switching frequency and periodic input charge vs. v in , v out ; i out = 8.33 a v pr vs. case temperature v in = 45 v; v out = 48 v 4.70 4.70 4.52 6.16 6.20 6.04 4 4.5 5 5.5 6 6.5 -40-20 0 20406080100 temperature [oc] v pr [v] 4.17 8.33 i out : figure 12 ? typical control node voltage vs. t case , i out ; v in = 45 v, v out = 48 v powertrain switching frequency and periodic output charge vs. input voltage - full load 800 825 850 875 900 925 950 975 1000 1025 38 40 42 44 46 48 50 52 54 56 input voltage [v] f sw [khz] 0 4 8 12 16 20 24 28 32 36 total output charge per switching cycle [ ? c] 55 20 48 55 20 48 v out f sw ? c figure 14 ? powertrain switching frequency and periodic output charge vs. v in , v out ; i out = 8.33 a dc safe operating area 0.00 2.08 4.17 6.25 8.33 10.42 5 1015202530354045505560 output voltage [v] output current [a] 0 80 160 240 320 400 output power [w] current power figure 16 ? dc output safe operating area rev. 1.1 12 / 2010 page 12 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 dc modulator gain and powertrain equivalent output resistance vs. output current - v out = 55v -4 -2 0 2 4 6 8 10 0123456789 output current [a] g pr [db] 0 50 100 150 200 250 r eq_out [ ? ] 38 45 55 38 45 55 v in : gpr r eq_out figure 17 ? powertrain characteristics vs. i out; resistive load, v out = 55 v, various v in dc modulator gain and powertrain equivalent output resistance vs. output current - v out = 48v -2 0 2 4 6 8 10 12 0123456789 output current [a] g pr [db] 0 10 20 30 40 50 60 70 80 90 r eq_out [ ? ] 38 45 55 38 45 55 v in : gpr r eq_out figure 19 ? powertrain characteristics vs. i out; resistive load, v out = 48 v, various v in output power vs. v pr v in = 45v, v out = 48v, t c =25oc 0 40 80 120 160 200 240 280 320 360 400 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 pr voltage [v] output power [w] typical min nominal typical max figure 21 ? output power vs. v pr ; v in = 45 v, v out = 48 v, t case = 25oc dc modulator gain and powertrain equivalent output resistance vs. output current - v out = 20v 2 4 6 8 10 12 14 0123456789 output current [a] g pr [db] 0 2 4 6 8 10 12 14 16 18 20 r eq_out [ ? ] 38 45 55 38 45 55 v in : gpr r eq_out figure 18 ? powertrain characteristics vs. i out; resistive load, v out = 20 v, various v in effective internal input (c in_int ) and output (c out_int ) capacitance vs. applied voltage 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 40 45 50 55 voltage [v] input capacitance [ f] 0 1 2 3 4 5 6 7 8 9 output capacitance [ f] cin cout figure 20 ? effective internal input and output capacitance vs. voltage ? ceramic type powertrain equivalent input resistance vs. output current - v out = 55v 0 2 4 6 8 10 12 14 16 0123456789 output current [a] r eq_in [ ? ] 38 45 55 v in : figure 22 ? magnitude of powertrain dynamic input impedance vs. v in , i out ; v out = 55 v rev. 1.1 12 / 2010 page 13 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 powertrain equivalent input resistance vs. output current - v out = 20v 0 10 20 30 40 50 60 70 80 90 0123456789 output current [a] r eq_in [ ? ] 38 45 55 v in : figure 23 ? magnitude of powertrain dynamic input impedance vs. v in , i out ; v out = 20 v powertrain equivalent input resistance vs. output current - v out = 48v 0 2 4 6 8 10 12 14 16 18 20 0123456789 output current [a] r eq_in [ ? ] 38 45 55 v in : figure 24 ? magnitude of powertrain dynamic input impedance vs. v in , i out ; v out = 48 v 8.0 general characteristics specifications apply over all line and load conditions, t j = 25 oc and output voltage from 20v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of -40 oc < t j < 125 oc (t-grade). attribute s y mbol min t y pmaxunit mechanical length l 32.3 / [1.27] 32.5 / [1.28] 32.8 / [1.29] mm / [in] width w 21.8 / [0.86] 22.0 / [0.87] 22.3 / [0.88] mm / [in] height h 6.60 / [0.26] 6.73 / [0.26] 6.86 / [0.27] mm / [in] volume vol 4.81 / [0.29] cm 3 / [in 3 ] weight w 13.6 g 0.51 2.03 0.02 0.15 0.003 0.051 thermal operating junction temperature t j -40 125 oc operating case temperature t c -40 100 oc thermal capacity 10 ws/oc assembly 6 lbs 5.41 lbs / in 2 storage temperature t st -40 125 oc 1000 400 soldering 245 oc 225 oc maximum time above [ 217] oc 150 s peak heating rate during reflow 1.5 2 oc / s peak cooling rate post reflow 2.5 3 oc / s reliability and agency approvals 2.29 mhrs 3.61 mhrs peak temperature during reflow under msl 5 conditions above under msl 6 conditions above peak compressive force applied to case (z-axis) supported by j-lead only msl 6, four hours out of bag maximum moisture sensitivity level msl msl 5 v agency approvals / standards esd rating human body model, "jedec jesd 22-a114c.01" charged device model, "jedec jesd 22-c101d" gold ? m no heatsink rohs 6 of 6 telcordia issue 2 - method i case 1; ground benign, controlled mil-hdbk-217plus parts count - 25c ground benign, stationary, indoors / computer profile c tuv us ce mark palladium nickel conditions / notes lead finish mtbf rev. 1.1 12 / 2010 page 14 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 9.0 product outline drawing and recommended pcb footprint rev. 1.1 12 / 2010 page 15 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 10.0 product details a nd design guidelines 10.1 control pins description and characteristics control node (pr) is the input to the control node which determines the powertrain timing and ultimately the module output power (figure 21). an internal 0.5ma current sink is always active. the bi-directional buffer between pr and the control node has two states. in normal operation, pr will be above the 0.79v switching threshold, and will drive the control node through the buffer. an internal 7.4v clamp determines the maximum output power that can be re quested of the modulator. when pr falls below 0.79 v, the converter will stop switching. an internal circuit clamps the modulator input control node to 0.79 v, and a buffer will source up to 2.5 ma out of the pin at that clam p level. for this reason, the output impedance of the amplif ier driving pr must be taken into account. a rail-to-rail operational amplifier with low output impedance is always recommended. the powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage, as shown in figures 17, 18 and 19. as the load increases, the powertrain pole moves to higher frequency. as a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. figure 25 shows a reference ac small-signal model. current feedback (if) is the input for the module output overcurrent protection and current limit features (see functional block diagram in section 4.0). a voltage proportional to the powertrain output current must be applied to if in order for overcurrent protection to operate properly. if the if voltage exceeds the if pin?s overcurrent protection threshold, the powertrain will stop switching. if the if voltage falls below the overcurrent protection threshold within t blank time, then the powertrain will immediately resumes switching. otherwise a fault is latched. the current limit threshold for the if pin is set lower than the protection threshold. w hen the if pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amp lifier which ov errides the modulator input maximum level. this causes the powertrain to maintain a constant output current. the bandwidth of this current limit integrator is significantly slower than that of the pr control node input. therefore this current limit can not be used in lieu of properly compensating the (external) pr control loop to avoid exceeding maximum current or power ratings for the device. if the if pin is not driven, it must be resistively terminated to sg. a 1k ? resistor to sg is recommended in this case. figure 25 ? PRM48BF480T400A00 ac small signal model rev. 1.1 12 / 2010 page 16 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 vtm control (vc) pin supplies an initial v cc voltage to downstream vtms, enabling them and synchronizing their startup with the prm. the v cc voltage is a pulse, typically 10ms duration at 14v. if vc is not loaded by a vtm, it must be terminated with a 1k ?? resistor to ?vout. primary control (pc) is both an input and an output. it can provide the following features: ? delayed start: upon application of voltage (>uvlo) to the module power input and after t off , the pc pin will source a constant 90 a current. ? output disable: pc may be pulled down externally in order to disable the module. pull down resistance should be less than 300 ? to sg. ? fault detection flag: the pc 5 v voltage source is internally turned off when a fault condition is latched. note that aside from the short circuit fault condition, pc does not have significant current sinking capability. therefore in the case of an array of prms with interconnected pc pins, pc does not in general reflect the fault state of all prms. the common pc line will not disable neighboring modules when a fault is detected except for a latched output short circuit fault. conversely any unit in the array latching a short circuit fault will disable the array for t scr . temperature monitor (tm) pin outputs a voltage proportional to the absolute temperature of the converter analog control ic. it can be used to accomplish the following functions: ? monitor the control ic temperature: the gain and setpoint of tm are such that the temperature, in kelvin, of the prm controller ic is equal to the voltage on the tm pin scaled by 100. (i.e. 3.0 v = 300 k = 27oc). ? closed loop thermal management at the system level (e.g. variable speed fans or coolant flow) ? fault detection flag: the tm voltage source is turned off as soon as a fault is detect ed. for system monitoring purposes (microcontroller interface) faults are detected on falling edges of tm. reference enable (re) pin outputs a regulated 3.3v, 8ma voltage source. it is enabled only after successful startup of the prm powertrain (see chapters 5.0 and 6.0.) re is intended to power t he output current transducer and also the voltage reference for the control loop. powering the reference generator with re helps provide a controlled startup, since the output voltage of the system is able to track the reference level as it comes up. voltage source (vs) pin outputs a gated (e.g. mirrors pc status), non-isolated, regulated 9v, 5ma voltage source. it can be used to power external control circuitry; it always leads re. signal ground (sg) pin provides a kelvin connection to the prm?s internal signal ground. it should be used as the reference for pr, tm, if, and should return all pc, vs and re pin currents. in array configurations with common ground control circuits, a series resistor (~1 ? ) is recommended in order to decouple power and signal current returns. 10.2 control circuit requirements and design procedure the PRM48BF480T400A00 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. these two external circuits are illustrat ed in figure 26, which shows an example of the prm in a standalone application with local voltage feedback and high side current sensing. in general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense ic. the following design procedures refer to the circuit shown in figure 26. 10.2.1 setting the output voltage level the output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. with reference to fig. 26, r1 and r2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference ic provides the reference voltage to the positive input of the error amplifier. under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: 2 2 1 r r r v v ref out ? ? ? note that the component r1 will also factor into the compensation as described in a later section. it is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. the recommended range for reference rise time is 1 ms to 9 ms. the lower rise time limit will ensure optimized modulator timing performance during startup, and to allow the current limit feature (through if pin) to fully protect the device during power-up. the upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream vtm input before the end of the vc pulse. rev. 1.1 12 / 2010 page 17 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 10.2.2 setting the output current limit and overcurrent protection level the current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. the output of the current sense ic provi des the if voltage which has v if_il and v if_oc thresholds for the two functions respectively. the set points are therefore defined by: cs s il if il g r v i ? ? _ and cs s oc if oc g r v i ? ? _ where g cs is the gain of the current sense amplifier. 10.2.3 control loop compensation requirements in order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. figure 25 shows the ac small signal model for the module. modulator dc gain g pr and powertrain equivalent resistance r eq_out are shown. these modeling parameters will support a design cut-off frequency up to 50khz. standard bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. the recommended stability criteria are as follows: 1) phase margin > 45o : for the closed loop response, the phase should be greater than 45o where the gain crosses 0db. 2) gain margin > 10db : the closed loop gain should be lower than -10db where the phase crosses 0o. 3) gain slope = -20db/decade : the closed loop gain should have a slope of -20db/decade at the crossover frequency. the compensation characteristics must be selected to meet these stability criteria. refer to figure 27 for a local sense, voltage-mode control example based on the configuration in figure 26. in this example, it is assumed that the maximum crossover frequency (f cmax ) has been selected to occur between b and c. type-2 compensation (curve ijkl) is sufficient in this case. the following data must be gathered in order to proceed: ? modulator gain g pr : see figures 17, 18, 19 ? powertrain equivalent resistance r eq : see figures 17, 18, 19 ? internal output capacitance: see figure 20 ? external output capacitance value in the case of ceramic capacitors, the esr can be considered low enough to push the associated zero well above the frequency of interest. applications with high esr capacitor may require a different type of compensation, or cascade control. the system poles and zeros of the closed loop can then be defined as follows: ? powertrain pole, assuming the external capacitor esr can be neglected: load out eq load out eq c r r r r r ext out ? ? ?? _ _ _ ? main pole frequency: ?? ext out int out load out eq load out eq p c r r r r _ _ _ _ c 2 1 f ? ? ? ? ? ? ? compensation mid-band gain: 1 3 mb r r log 20 g ? [1] ? compensation zero: 1 3 1 z c r 2 1 f ? ? ? [2] ? compensation pole: 2 1 2 1 3 2 2 1 f c c c c r p ? ? ? ? ? and for f p2 >>f z1 (c 1 + c 2 c 1 ): 2 3 2 2 1 f c r p ? ? ? ? [3] rev. 1.1 12 / 2010 page 18 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 10.2.4 midband gain design (r1,r3): with reference to figure 27: curve abc is the: ? minimum output voltage in the application ? maximum input voltage expected in the application ? maximum load prm open loop response, and is where the maximum crossover frequency occurs. in order for the maximum crossover frequency to occur at the design choice f cmax , the compensation gain must be equal and opposite of the powertrain gain at this freque ncy. for stability purposes, the compensation should be in the mid-band (j-k) at the crossover. using equation [1], the mid-band gain can be selected appropriately. 10.2.5 compensation zero design (c1): with reference to figure 27: curve efg is the: ? maximum output voltage in the application ? minimum input voltage expected in the application ? minimum load in the application prm open loop response, and is where the minimum crossover frequency f cmin occurs. based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore f cmin will occur where efg is equal and opposite of g mb . c1 can be selected using equation [2] so that f z1 occurs prior to f cmin . figure 26 ? control circuit example prm tm regulator rev. 1.1 12 / 2010 page 19 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 open loop gain vs. frequency -40 -20 0 20 40 60 80 frequency, log scale (y-intercept is application specific) gain (db) prm open loop max load a b e f i j k l compensation gain a pplication's op-amp gbw c g f cmax f cmin prm open loop min load figure 27 ? reference asymptotic bode pl ot for the considered system 10.2.6 high frequency pole design (c2): using equation [3], c2 should be selected so that f p2 is at least one decade above f cmax and prior to the gain bandwidth product of the operat ional amplifier (10mhz for this example). for applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. 10.2.7 verifying stability: the preferred method for veri fying stability is to use a network analyzer, measuring the closed loop response across various lines and load conditions. in the absence of a network analyzer, a load step transient response can be used in order to estimate stability. figure 28 illustrates an exampl e of a load step response. equation [4] can be used to predict the phase margin based on the ratio of the ?kick? to ?droop? (as defined in fig. 28). figure 28 ? load step response example and ?droop? vs. ?kick? definition rev. 1.1 12 / 2010 page 20 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 2 2 2 ln ln 100 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d k d k m [4] 10.3 burst mode operation: at light loads, the prm will operate in a burst mode due to minimum timing constraints. an example burst operation waveform is illustrated in figure 29. for very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. in this case the external error amplifier will periodically drive pr below the switching threshold in order to maintain regulation. switching will cease momentarily until the error amplifier once again drives pr volt age above the threshold. figure 29 ? light load burst mode of operation note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. the variability depends on many factors including input voltage, output voltages, load impedance, and external error amplifier output impedance. in burst mode, the gain of the pr input to the plant which is modeled in the previous sections is time varying. therefore the small signal analysis can not be directly applied to burst mode operation. 10.4 input and output filter design figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the prm at full load under various input and output voltages conditions. figure 20 provides the effective internal capacitance of the module. a conservative estimate of input and output peak- peak voltage ripple at nominal line and trim is provided by equation [5]: ext int sw fl tot c c f i q v ? ? ? ? ? 4 . 0 [5] q tot is the total input (fig. 15) or output (fig. 14) charge per switching cycle at full load, while c int is the module internal effective capacitance at the considered voltage (fig. 20) and c ext is the external effective capacitance at the considered voltage. 10.5 input filter stability the prm can provide very high dynamic transients. it is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. for this purpose, the converter dynamic input impedance magnitude in eq r _ is provided in figures 22, 23, 24. it is recommended to provide adequate design margin with respect to the st ability conditions illustrated in 10.5.1 and 10.5.2 . 10.5.1 inductive source and local, external input decoupling capacitance with negligible esr (i.e.: ceramic type) the voltage source impedance can be modeled as a series r line l line circuit. the high performance ceramic decoupling capacitors will not significantly damp the network because of their low esr; therefore in order to guarantee stability the following conditions must be verified: in eq ext in int in line line r c c l r _ _ _ ) ( ? ? ? [6] in eq line r r _ ?? [7] it is critical that the line source impedance be at least an octave lower than the converter?s dynamic input resistance, [7]. however, r line cannot be made arbitrarily low otherwise equation [6] is violated and the system will show instability, due to under-damped rlc input network. rev. 1.1 12 / 2010 page 21 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 10.5.2 inductive source and local, external input decoupling capacitance with significant r cin_ext esr (i.e.: electrolytic type) in order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor l line . notice that, the high performance ceramic capacitors c in_int within the prm should be included in the external electrolytic capacitance value for this purpose. the stability criteria will be ext in c in eq r r _ _ ? [8] in eq c ext in line r r c l ext in _ _ _ ? ? [9] equation [9] shows that if the aggregate esr is too small ? for example by using very high quality input capacitors (c in_ext ) ? the system will be under-damped and may even become destabilized. again, an oc tave of design margin in satisfying [8] should be considered the minimum. 10.6 arrays up to ten prms of the same type may be placed in parallel to expand the power capacity of the system. the following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. ? ?in pins of all prms must be connected together. both inductance and resistance from the common power source to each prm should be minimized, and matched. ? input voltage to all prms must be the same. independent fuses for each prm are recommended. ? pc pins must be connected together for synchronization and proper fault response. ? reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules? re pins have reached their operational voltage levels. ? there must be one single external voltage control loop. the control loop must drive each pr pin relative to each modules? sg pin, and the local pr voltage must be the same across all modules. ? each prm must have its own local current shunt and current sense circuitry to drive it?s if pin. ? the number of prms required to achieve a given array capacity must consider all sources of mismatch to avoid overstress of any prm in the array. imbalances in sharing are not only due to current sharing accuracy specifications, but also temperature differences among prms, vin variations, and error terms in the buffering of the error amplifier output to the pr pins. ? control loop compensation procedures above will hold for an array, in general, although many parameters must be scaled against the number of prms in the system. please contact vicor applications for assistance. 10.7 input fuse recommendations a fuse should be incorporated at the input to each prm, in series with the +in pin. a 15a or smaller input fuse (littelfuse ? nano 2? 451/453 series, or equivalent) is required to safety agency conditions of acceptability. always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. 10.8 layout considerations application note an:005 details board layout using v?i chip components. additional consideration must be given to the external control circuit components. the current sense shunt signal voltage is highly sensitive to noise. as such, current sensing circuitry should be located close to the shunt to minimize the length of the sense signals. a kelvined connection at the shunt is recommended for best results. the control signal from a remote voltage sense circuit to the prm should be shielded. avoid routing this, or other control signals directly underneath the prm, if possible. components that tie directly to the prm should be located close to their respective pins. it is also critical that all control components be referenced to sg, and that sg not be tied to any other ground in the system, including ?in or ?out of the prm. rev. 1.1 12 / 2010 page 22 of 22 PRM48BF480T400A00 ( formerl y v ip0001tfj ) v?i chip corp. (a vicor company) 25 frontage rd. andover, ma 01810 800-735-6200 warranty vicor products are guaranteed for two years from date of sh ipment against defects in material or workmanship when in normal use and service. this warranty does not extend to produc ts subjected to misuse, accident, or improper application or maintenance. vicor shall not be liable for collateral or cons equential damage. this warranty is extended to the original purchaser only. except for the foregoing express warranty, vicor makes no warranty, express or implied, including, but not limited to, the warranty of merchantability or fitness for a particular purpose. vicor will repair or replace defective products in accordance with its own best judgment. for service under this warranty, the buyer must contact vicor to obtain a return material au thorization (rma) number and sh ipping instructions. products returned without prior authorization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all reshipment charges if the product was defective within the terms of this warranty. information published by vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. vicor does not assume any liabi lity arising out of the applicat ion or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. vicor general policy does not recommend the use of its components in life support applicati ons wherein a failure or malfunction may directly threaten life or injury. per vicor terms and conditions of sale, the us er of vicor components in life support applications assumes all risks of such use and indemn ifies vicor against all damages. vicor?s comprehensive line of power solutions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and re liable. however, no responsibility is assumed by vicor for its use. vicor components are not designed to be used in applic ations, such as life support sy stems, wherein a failure or malfunction could result in injury or d eath. all sales are subject to vicor?s terms and conditions of sale, which are available upon request. specifications are subject to change without notice. intellectual property notice vicor and its subsidiaries own intellectual property (inc luding issued u.s. and foreign patents and pending patent applications) relating to the products described in this data sheet. interested parties should contact vicor's intellectual property department. the products described on this data sheet are protec ted by the following u. s. patents numbers: 5,945,130; 6,403,009; 6, 710,257; 6,911,848; 6,930,89 3; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,84 4; d496,906; d505,114; d5 06,438; d509,472; and for use under 6,975, 098 and 6,984,965. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email customer service: custserv@vicorpower.com technical support: apps@vicorpower.com |
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